1. Field of the Invention
The present invention relates to a systolic array processor which is adapted to virtually constitute a number of analog type pipelining processors which operate in a parallel manner on an analog type shift register array such as a CCD (charge coupled device) or the like.
2. Prior Art
Heretofore, in a processing of analog signals using a DSP (digital signal processor) or the like, a pipelining process is broadly adopted for the purpose of processing signals at a high speed, and the pipeline process produces an arithmetic operation of a much higher accuracy as compared with pure analog processing and also permits processing in a region of relatively low frequency such as an audio signal or the like.
A separate device for parallel processing for higher processing speed is indispensable for processing of enormous or extensive data such as a real time processing of a video signal or the like. However, it is difficult in practice to perform a relatively complicated processing mainly because of economics, such as the cost of an arithmetic unit.
On the other hand, in case of "a parallel analog signal processing using a resistor network" the study of which goes on progressing in a field of artificial retina called "vision chip" or the like, there is an advantage that signal processing can be performed at a high speed by small-sized hardware by performing the signal processing for analog signals on the resistor network without any A/D or D/A conversion. However, the function thereof tends to be limited and it appears to be a disadvantage that the setting of characteristics thereof cannot be done so freely as in DSP.
Also, for the purpose of a signal processing for a specific use such as Fourier transform is practically used a digital type systolic array in which many digital arithmetic devices are arranged in a mesh configuration and two-dimensional pipeline processing is performed. However, in order to meet analog input signals having a high possibility of being applied in parallel, many analog-digital (A/D) converter means are naturally needed and this is a defect in improving the performance thereof economically and further lack of flexibility in application is an important problem.
The present invention intends to provide an analog systolic array processor which brings to realization of a two-dimensional pipelining processor wherein signal processing for a sum of product operation or the like in analog domain can be done in parallel by performing signal processing such as multiplications between digital signals and analog signals having a high possibility of being applied in parallel such as video information without any conversion of the analog signals and by effecting successive addition of the result of the signal processing to an addition node moving on an analog shift register at a proper timing.